Publications

You can find the full list of my articles on my Google Scholar profile.

Selected Publications

• Jangryul Kim, Kangkyu Park, Hoeseok Yang, and Soonhoi Ha, “Adaptive run-time scheduling of dependent services for service-oriented IoT systems,” Design Automation for Embedded Systems, Volume 25, Pages 265–295, July 07, 2021. [link]
• Hyung-Chan An and Hoeseok Yang, “Fully Adaptive Stochastic Handling of Soft-Errors in Real-Time Systems,” IEEE Access, Volume 9, Pages 155058-155071, November 16, 2021. [link]
• Kyusik Choi and Hoeseok Yang, “A GPU Architecture Aware Fine-Grain Pruning Technique for Deep Neural Networks,” in Proceedings of European Conference on Parallel Processing (Euro-Par 2021), Pages 217-231, September 1, 2021. [link]
• Dasom Lee, Hyeonseok Jeong, and Hoeseok Yang, “Real-Time Schedulability Analysis and Enhancement of Transiently Powered Processors With NVMs,” IEEE Transactions on Computers, Volume 70, No. 3, Pages 372-383, March 1 2021. [link]
• Beomsik Kim and Hoeseok Yang, “Reliability optimization of real-time satellite embedded system under temperature variations,” IEEE Access, Volume 8, Pages 224549-224564, December 14, 2020. [link]
• Junchul Choi, Hoeseok Yang, and Soonhoi Ha, “Optimization of Fault-Tolerant Mixed-Criticality Multi-Core Systems with Enhanced WCRT Analysis,” ACM Transactions on Design Automation of Electronic Systems, Volume 24, Issue 1, Article No.: 6, pp 1–26, January 2019 [link]
• Hyeonseok Jung and Hoeseok Yang, “Context-aware dataflow adaptation technique for low-power multi-core embedded systems,” in Proceedings of the 55th ACM/ESDA/IEEE Design Automation Conference (DAC), pages 1-6, June 24, 2018. [link]
• Shin-haeng Kang, Duseok Kang, Hoeseok Yang, and Soonhoi Ha, “Real-time co-scheduling of multiple dataflow graphs on multi-processor systems,” in Proceedings of the 53rd ACM/ESDA/IEEE Design Automation Conference (DAC), pages 1-6, June 5, 2016. [link]
• Hyung-Chan An, Hoeseok Yang, and Soonhoi Ha, “A formal approach to power optimization in cpss with delay-workload dependence awareness,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 35, No. 5, Pages 750-763, February 11, 2016. [link]
• Pengcheng Huang, Hoeseok Yang, and Lothar Thiele, “On the scheduling of fault-tolerant mixed-criticality systems,” in Proceedings of the 51st ACM/EDAC/IEEE Design Automation Conference (DAC), page 1-6, June 2014. [link]
• Shin-haeng Kang, Hoeseok Yang, Sungchan Kim, Iuliana Bacivarov, Soonhoi Ha, and Lothar Thiele, “Static mapping of mixed-critical applications for fault-tolerant MPSoCs,” in Proceedings of the 51st ACM/EDAC/IEEE Design Automation Conference (DAC), page 1-6, June 2014. [link]
• Shin-haeng Kang, Hoeseok Yang, Sungchan Kim, Iuliana Bacivarov, Soonhoi Ha, and Lothar Thiele, “Reliability-aware mapping optimization of multi-core systems with mixed-criticality,” in Proceedings of 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), March 2014. [link]
• Hoeseok Yang, Iuliana Bacivarov, Devendra Rai, Jian-Jia Chen, and Lothar Thiele, “Real-time worst-case temperature analysis with temperature-dependent parameters,” Real-Time Systems, Volume 49, Issue 6, Pages 730-762, November 2011.
• Lars Schor, Hoeseok Yang, Luliana Bacivarov, and Lothar Thiele, “Expandable process networks to efficiently specify and explore task, data, and pipeline parallelism,” in Proceedings of 2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), September 2013. [link]
• Shin-Haeng Kang, Hoeseok Yang, Lars Schor, Iuliana Bacivarov, Soonhoi Ha, and Lothar Thiele, “Multi-objective mapping optimization via problem decomposition for many-core systems,” in Proceedings of 2012 the 10th Symposium on Embedded Systems for Real-time Multimedia (ESTIMedia), Pages 28-37, October 2012. [link]
• Devendra Rai, Hoeseok Yang, Iuliana Bacivarov, and Lothar Thiele, “Power agnostic technique for efficient temperature estimation of multicore embedded systems,” in Proceedings of the 2012 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), October 2012. [link]
• Lars Schor, Iuliana Bacivarov, Devendra Rai, Hoeseok Yang, Shin-Haeng Kang, and Lothar Thiele, “Scenario-based design flow for mapping streaming applications onto on-chip many-core systems,” in Proceedings of the 2012 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), Pages 71-80, October 2012. [link]
• Lars Schor, Iuliana Bacivarov, Hoeseok Yang, and Lothar Thiele, “Worst-case temperature guarantees for real-time applications on multi-core systems,” in Proceedings of the 2012 IEEE 18th Real Time and Embedded Technology and Applications Symposium (RTAS), Pages 87-96, April 2012. [link]
• Lothar Thiele, Lars Schor, Hoeseok Yang, and Iuliana Bacivarov, “Thermal-aware system analysis and software synthesis for embedded multi-processors,” in Proceedings of the 48th Design Automation Conference (DAC), Pages 268-273, June 2011. [link]
• Devendra Rai, Hoeseok Yang, Iuliana Bacivarov, Jian-Jia Chen, and Lothar Thiele, “Worst-case temperature analysis for real-time systems,” in Proceedings of the 2011 Design, Automation & Test in Europe (DATE), March 2011. [link]
• Hoeseok Yang, Sungchan Kim, and Soonhoi Ha, “An MILP-based performance analysis technique for non-preemptive multitasking MPSoC,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 29, Issue 10, Pages 1600-1613, September 2010. [link]
• Hoeseok Yang and Soonhoi Ha, “Pipelined data parallel task mapping/scheduling technique for MPSoC,” in Proceedings of the 2009 Design, Automation & Test in Europe Conference & Exhibition (DATE), Pages 69-74, April 2009. [link]
• Hoeseok Yang and Soonhoi Ha, “ILP based data parallel multi-task mapping/scheduling technique for MPSoC,” in Proceedings of the 2008 International SoC Design Conference (ISOCC), Pages 134-137, November 2008. [link]
• Hyunuk Jung, Hoeseok Yang, and Soonhoi Ha, “Optimized RTL code generation from coarse-grain dataflow specification for fast HW/SW cosynthesis,” Journal of Signal Processing Systems, Volume 52, Issue 1, Pages 13-34, July 2008. [link]